1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby.
2. Description of the Related Art
As electronic products employing semiconductor devices become lightweight and small in size, a high integration density per unit area, a low threshold voltage Vth, a fast operating speed and low power consumption are required for the semiconductor devices. Discrete devices such as metal oxide semiconductor (MOS) transistors are widely employed as switching devices for the semiconductor devices. In response to requirements for the high integration density as described above, methods of stacking a plurality of transistors on a limited area of a semiconductor substrate have been researched. The method of stacking the transistors includes forming a lower transistor on the semiconductor substrate, forming an insulating layer for covering the lower transistor, and forming a thin film transistor on the insulating layer. However, the method of stacking the transistors is accompanied by several difficulties.
Semiconductor devices having TFTs stacked on a semiconductor substrate are disclosed in U.S. Pat. No. 6,022,766, entitled “Semiconductor Structure Incorporating Thin Film Transistors and Methods for Its Manufacture” to Chen et al.
FIG. 1 is a cross-sectional view illustrating a structure of the stacked transistors in accordance with U.S. Pat. No. 6,022,766.
Referring to FIG. 1, a typical bulk transistor is formed on a single crystal silicon substrate, and a thin film transistor is stacked on the bulk transistor. An interlayer insulating layer and a cap oxide layer 189 are sequentially interposed between the bulk transistor and the thin film transistor. The thin film transistor includes a body layer formed on the cap oxide layer 189. The body layer is divided into source and drain regions 190A and 190B and a channel region 196. A gate electrode 194A is formed over the channel region 196. A gate insulating layer 192 is interposed between the gate electrode 194A and the body layer. An upper insulating layer is formed to cover the entire surface of the semiconductor substrate including the gate electrode 194A.
Studs 182 and 184 are formed on the source and drain regions of the bulk transistor. One of the source and drain regions of the bulk transistor is electrically connected to one of the source and drain regions 190A and 190B of the thin film transistor via the stud 182 and an interfacial cap 188A formed on the stud 182.
The body layer of the thin film transistor is formed by forming an amorphous silicon layer on the entire surface of the semiconductor substrate having the studs 182 and 184 and the interfacial cap 188A and crystallizing the amorphous silicon layer using an annealing process. In this case, the body layer corresponds to a polysilicon layer having great grains. That is, it is difficult to transform the body into a completely single crystal silicon layer. Consequently, it is difficult to form the thin film transistor having the electrical characteristics corresponding to that of the bulk MOS transistor.
Other semiconductor devices having stacked transistors on a semiconductor substrate are disclosed in U.S. Pat. No. 6,429,484 B1 entitled “Multiple Active Layer Structure and A Method of Making Such a Structure” to Yu.
According to Yu, an interlayer insulating layer is formed on a semiconductor substrate, and a window penetrating the interlayer insulating layer is formed to expose the semiconductor substrate. An amorphous semiconductor layer is formed to completely fill the window and cover the interlayer insulating layer. The amorphous semiconductor layer is crystallized using a solid phase epitaxial (SPE) technique. As a result, a single crystal semiconductor plug is formed within the window, and a single crystal semiconductor body is formed on the interlayer insulating layer.
However, when impurity ions are implanted into the single crystal semiconductor plug, it may have conductivity. Accordingly, there is a limitation in determining a position for forming the window when an insulating characteristic is required between the single crystal semiconductor body and the semiconductor substrate.